Phase locked loops (PLLs) are a class of devices that match the phase and frequency of a reference clock signal with the phase and frequency of an output clock signal. PLLs are widely used in frequency modulation (FM) radio, frequency synthesis, and digital computing applications.
In digital computing applications, PLLs are used to synchronize various clock signals with a master clock signal. For instance, a pair of PLLs can synchronize a data processor's operations with the operations of a separate memory system. In this case, a PLL in the data processor and a PLL in the memory system both receive a master clock signal, typically generated by a crystal oscillator. The output clock signal of the data processor PLL is routed to every clocked latch in the data processor. Similarly, the output clock signal of the memory system PLL is routed to every clocked latch in the memory system. The operations of the data processor and the memory system are thereby synchronized.
Lock time is one characteristic of PLLs. Lock time for a particular PLL is the time period beginning with PLL power-on and ending once the PLL realigns its output clock signal with its input clock signal. A PLL output clock signal of a PLL can not be used during its lock time because it is not identical to the input clock signal. As a consequence, PLLs used in time critical applications often are never turned off. However, in digital computing applications, power consumption is often as serious a limitation as performance. The distribution of a PLL's output clock signal to every clocked latch in a data processor consumes a relatively large amount of power whether or not the latches are performing useful operations. Therefore, the limitations of PLL power consumption and performance are often in opposition in data processing applications.